1 idt49fct805/a fast cmos buffer/clock driver commercial and industrial temperature range march 2006 2006 integrated device technology, inc. dsc-5836/5 c idt49fct805/a commercial and industrial temperature range fast cmos buffer/clock driver functional block diagram features: ? 0.5 micron cmos technology ? guaranteed low skew < 700ps (max.) ? low duty cycle distortion < 1ns (max.) ? low cmos power levels ? ttl compatible inputs and outputs ? rail-to-rail output voltage swing ? high drive: -24ma i oh , +64ma i ol ? two independent output banks with 3-state control ? 1:5 fanout per bank ? "heartbeat" monitor output ? available in ssop and soic packages the idt logo is a registered trademark of integrated device technology, inc. description: the 49fct805 is a non-inverting buffer/clock driver built using ad- vanced dual metal cmos technology. each bank consists of two banks of drivers. each bank drives five output buffers from a standard ttl compatible input. these devices feature a ?heart-beat? monitor for diagnostics and pll driving. the mon output is identical to all other outputs and complies with the output specifications in this document. the 49fct805 offers low capacitance inputs and hysteresis. rail-to-rail output swing improves noise margin and allows easy interface with cmos inputs. in a in b oe b oe a oa 1 -oa 5 ob 1 -ob 5 mon 5 5
2 commercial and industrial temperature range idt49fct805/a fast cmos buffer/clock driver v cca oa 1 oa 2 gnd a (1) in a 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 oa 3 oa 4 oa 5 oe a v cc ob 1 gnd b mon in b ob 2 ob 3 ob 4 ob 5 oe b nc note: 1. pin 8 is not internally connected on devices with a "k" prefix in the date code. on older devices, pin 8 is internally connected to gnd. to insure compatibility with all products, pin 8 should be connected to gnd at the board level. pin description pin names description oe a , oe b 3-state output enable inputs (active low) in a , in b clock inputs oan, obn clock outputs m o n monitor output function table (1) inputs outputs oe a , oe b in a , in b oan, obn mon llll lhhh hlzl hh zh note: 1. h = high l = low z = high-impedance absolute maximum ratings (1) symbol description max unit v term (2) terminal voltage with respect to gnd ?0.5 to +7 v v term (3) terminal voltage with respect to gnd ?0.5 to v cc +0.5 v t stg storage temperature ?65 to +150 c i out dc output current ?60 to +60 ma notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. input and v cc terminals. 3. output and i/o terminals. capacitance (t a = +25 o c, f = 1.0mhz) symbol parameter (1) conditions typ. max. unit c in input capacitance v in = 0v 4.5 6 pf c out output capacitance v out = 0v 5.5 8 pf note: 1. this parameter is measured at characterization but not tested. pin configuration soic/ ssop top view
3 idt49fct805/a fast cmos buffer/clock driver commercial and industrial temperature range dc electrical characteristics over operating range following conditions apply unless otherwise specified: v lc = 0.2v; v hc = v cc - 0.2v commercial: t a = 0c to +70c, industrial: t a = -40c to +85c, v cc = 5v 5% symbol parameter test conditions (1) min. typ. (2) max. unit v ih input high level (input pins) guaranteed logic high level 2 ? ? v v il input low level (input and i/o pins) guaranteed logic low level ? ? 0.8 v i ih input high current v cc = max. v i = 5.5v ? ? 1a i il input low current v cc = max. v i = gnd ? ? 1a i ozh off state (hi-z) output current v cc = max. v o = v cc ?? 1a i ozl v o = gnd ? ? 1 v ik clamp diode voltage v cc = min., i in = ?18ma ? ?0.7 ?1.2 v i os short circuit current v cc = max., v o = gnd (3) ?60 ?120 ? ma v cc = 3v, v in = v lc or v hc i oh = ?32 av hc v cc ? v oh output high voltage v cc = min. i oh = ?300 av hc v cc ?v v in = v ih or v il i oh = ?15ma 3.6 4.3 ? i oh = ?24ma 2.4 3.8 ? v cc = 3v, v in = v lc or v hc i ol = 300 a ? gnd v lc v ol output low voltage v cc = min. i ol = 300ma ? gnd v lc v v in = v ih or v il i ol = 64ma ? 0.3 0.55 v h input hysteresis for all inputs ? ? 200 ? mv i cc quiescent power supply current v cc = max., v in = gnd or v cc ? 5 500 a notes: 1. for conditions shown as max. or min., use appropriate value specified under electrical characteristics for the applicable dev ice type. 2. typical values are at vcc = 5v, +25c ambient. 3. not more than one output should be shorted at one time. duration of the test should not exceed one second.
4 commercial and industrial temperature range idt49fct805/a fast cmos buffer/clock driver notes: 1. for conditions shown as max. or min., use appropriate value specified under electrical characteristics for the applicable dev ice type. 2. typical values are at v cc = 5v, +25c ambient. 3. per ttl driven input (v in = 3.4v); all other inputs at v cc or gnd. 4. this parameter is not directly testable, but is derived for use in total power supply calculations. 5. values for these conditions are examples of the i c formula. these limits are guaranteed but not tested. 6. i c = i quiescent + i inputs + i dynamic i c = i cc + i cc d h n t + i ccd (f o n o ) i cc = quiescent current (i ccl , i cch and i ccz ) i cc = power supply current for a ttl high input (v i n = 3.4v) d h = duty cycle for ttl inputs high n t = number of ttl inputs at d h i ccd = dynamic current caused by an input transition pair (hlh or lhl) f o = output frequency n o = number of outputs at f o all currents are in milliamps and all frequencies are in megahertz. power supply characteristics symbol parameter test conditions (1) min. typ. (2) max. unit i cc quiescent power supply current v cc = max. ? 1 2.5 ma ttl inputs high v in = 3.4v (3) i ccd dynamic power supply current (4) v cc = max. v in = v cc ? 0.15 0.2 ma/mhz outputs open v in = gnd oe a = oe b = gnd 50% duty cycle i c total power supply current (6) v cc = max. v in = v cc ? 1.5 2.5 outputs open v in = gnd f o = 10mhz 50% duty cycle v in = 3.4v ? 2 3.8 oe a = oe b = v cc v in = gnd mon. output toggling v cc = max. v in = v cc ? 4.1 6 (5) ma outputs open v in = gnd f o = 2.5mhz 50% duty cycle v in = 3.4v ? 5.1 8.5 (5) oe a = oe b = gnd v in = gnd eleven outputs toggling
5 idt49fct805/a fast cmos buffer/clock driver commercial and industrial temperature range notes: 1. propagation delay range indicated by min. and max. limit is due to v cc , operating temperature and process parameters. these propagation delay limits do not imply skew. 2. see test circuits and waveforms. switching characteristics over operating range (1) fct805 fct805a symbol parameter conditions (2) min . max . min . max . unit t plh propagation delay c l = 50pf 1.5 5.6 1.5 5.3 ns t phl in a to oan, in b to obn r l = 500 t r output rise time ? 1.5 ? 1.5 ns t f output fall time ? 1.5 ? 1.5 ns t sk(o) output skew: skew between outputs of all banks of ? 0.7 ? 0.7 ns same package (inputs tied together) t sk(p) pulse skew: skew between opposite transitions ? 1 ? 1 ns of same output (|t phl -? t plh |) t sk(pp) part-to-part skew: skew between outputs of different ? 1.5 ? 1.5 ns packages at same power supply voltage, temperature, package type and speed grade t pzl output enable time 1.5 8 1.5 8 ns t pzh oe a to oan, oe b to obn t plz output disable time 1.5 7 1.5 7 ns t phz oe a to oan, oe b to obn
6 commercial and industrial temperature range idt49fct805/a fast cmos buffer/clock driver 7v v cc pulse generator d.u.t. 500 500 r t v in v out 50pf c l 0v v oh t plh t phl v ol t r 3v 1.5v t f 2.0v 0.8v 1.5v output input control input t plz 0v output normally low t pzh 0v switch closed output normally high enable disable switch open t phz 0v v ol v oh 0.3v 0.3v 1.5v 1.5v t pzl 3.5v 3.5v 3v 1.5v 0v v oh t plh t phl v ol 3v 1.5v 1.5v output input t sk (p) = t phl - t plh 0v v oh t plh1 v ol 1.5v output 1 3v 1.5v input v oh t sk(o) v ol 1.5v t sk (o) = t plh2 - t plh1 or t phl2 - t phl1 output 2 t plh1 t sk(o) t plh2 t phl2 0v v oh t plh1 v ol 1.5v package 1 output 3v 1.5v input v oh t sk(pp) v ol 1.5v t sk (pp) = t plh2 - t plh1 or t phl2 - t phl1 t phl1 t sk(pp) t plh2 t phl2 package 2 output package delay test circuits and waveforms pulse skew - t sk(p) test circuits for all outputs definitions: c l = load capacitance: includes jig and probe capacitance. r t = termination resistance: should be equal to z out of the pulse generator. test switch disable low closed enable low disable high gnd enable high switch position enable and disable times output skew part-to-part skew - t sk(pp) notes: 1. diagram shown for input control enable-low and input control disable-high 2. pulse generator for all pulses: rate 1.0mhz; t f 2.5ns; t r 2.5ns note: 1. package 1 and package 2 are same device type and speed grade.
7 idt49fct805/a fast cmos buffer/clock driver commercial and industrial temperature range ordering information idt49fct x package so sog py pyg small outline ic soic - green shrink small outline package ssop - green 805 805a fast cmos buffer/clock driver xxxx device type x process blank i commercial (0c to +70c) industrial (-40c to +85c) corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or 408-284-8200 clockhelp@idt.com san jose, ca 95138 fax: 408-284-2775 www.idt.com
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